Tech Logic

TSMC Expands Advanced Packaging Capacity: Two New Plants in Chiayi, Arizona Plans Move Forward

According to three sources, TSMC is expanding its advanced chip packaging capacity: Reuters says it will add two advanced packaging plants in Chiayi Science Park in Taiwan; another source says TSMC plans to build an advanced packaging plant in Arizona and has already started construction; a third source says Phase 2 in Chiayi is also seeing three advanced packaging facilities under construction. The sources agree on the core direction of advanced packaging expansion, but differ on plant counts, locations, and project timelines, and some key details cannot be confirmed from the provided sources.

Jul 15, 2026

CXMT Secures Major Tencent Memory Chip Supply Deal During STAR Market IPO Push, as All Three Sources Point to Domestic Substitution and Demand Expansion

According to cross-checking across three sources, while CXMT was advancing its STAR Market IPO, it was reported to have reached a long-term memory chip supply agreement with Tencent worth more than RMB 20 billion. Another source interpreted the listing from an industry perspective as linked to China’s push for self-reliance in memory chips and reduced dependence on external capital and technology. Claims in one source about “14 agreements” and roughly US$100 billion in RPO cannot be confirmed from the provided sources.

Jul 1, 2026

Intel 18A-P Enters Trial Production: Confirmed PPA Gains and Unverified Detail Boundaries

Intel has announced that its 18A-P manufacturing process has entered the test/risk production stage. The core fact confirmed by three sources is that the node continues to build on 18A and is described as superior to 18A in power, performance, and area (PPA); one source provides specific figures, saying it delivers a 9% performance improvement at the same power level and an 18% reduction in power consumption. One source also mentions enhancements to GAA and backside power delivery (BSPD/Backside Power Delivery) technologies. However, the event summary’s references to PowerBoost, 0.5V, CFET, and a broader roadmap could not be confirmed from the provided sources.

Jun 24, 2026

HKU Team Unveils Cryogenic Brain-Inspired Chip Research: SiC Transistor Simulates Neuronal Spikes at 10 mK

A University of Hong Kong team has announced research based on a Nature Communications paper, reporting a cryogenic neuromorphic circuit in silicon carbide (SiC) MOSFETs that can operate in ultra-low-temperature environments. A single transistor can mimic neuronal spiking behavior, with potential applications in quantum computing control and deep-space exploration electronics. Three sources are broadly consistent on the paper title, materials, research leaders, and the core low-temperature NDR/spiking behavior. Claims such as “world-first” and the exact scope of applications are presented with promotional differences in some sources, and no further quantifiable data were provided for verification.

Jun 13, 2026

Microsoft unveils second-generation topological quantum chip Majorana 2, says qubit lifespan has increased by about 1,000 times and points to commercialization in 2029

Microsoft has announced its second-generation topological quantum chip, Majorana 2. All three sources confirm the core claims: qubit lifespan is about 1,000 times longer than in the first generation, averaging around 20 seconds and reaching up to one minute in some cases; the company is also pointing to 2029 as the timeline for scalable, commercially viable quantum computers. Based on the provided sources, the TSO verification conclusion is that the three sources are highly consistent on the key facts, but Sources 1 and 2 do not provide verifiable background details, and the concerns about reproducibility and the lack of peer review appear only in the event summary and cannot be confirmed from the given sources.

Jun 5, 2026

Huawei Introduces the Tau Scaling Law: Pursuing New Paths to Improve Chip Efficiency Through Advanced Packaging, 3D Stacking, and Logic Layering

At the end of May 2026, Huawei publicly explained its new chip concept, the “Tau Scaling Law” or “Tau Law,” emphasizing that it would no longer rely solely on continued transistor miniaturization, but instead improve chip density, performance, and efficiency through advanced packaging, 3D stacking, and LogicFolding. Reuters and The Wall Street Journal both confirmed this direction; related DIGITIMES coverage mentioned the role of glass substrates in this approach, although the main article did not directly expand on Huawei’s chip technology. Some details, such as whether glass substrates are central and the exact scope of industry impact, could not be fully confirmed from the available sources.

Jun 4, 2026